1. Technical Field
The present disclosure relates to an integrated circuit (IC) apparatus, and more particularly, to a mixed-voltage input/output (I/O) circuit for interfacing apparatuses having different operating voltages and an IC apparatus including the same.
2. Discussion of Related Art
In complementary metal-oxide semiconductor (CMOS) technology, a supply voltage is scaled down to reduce power consumption and the dimensions of a transistor are also scaled down to improve circuit performance and area efficiency. Some semiconductor chips in a microelectronic system are implemented using different CMOS techniques and cannot use the same voltage, and therefore, a mixed-voltage I/O interface is needed. For instance, a read voltage of a dynamic random access memory (DRAM) chip is 2.5 V for 80 nm DRAM half-pitch but is 2.0 V for 60 nm DRAM half-pitch.
When a conventional non-mixed interfacing method is used in a mixed-voltage system, generation of unwanted leakage current, decrease in the reliability of a gate oxide, and hot-carrier injection may occur.
In a receiving mode for receiving an external signal, the voltage of an I/O pad may be higher than a power supply voltage, and therefore, an unwanted leakage current path may be formed from the I/O pad to a power supply through a pull-up P-type metal-oxide semiconductor (PMOS) transistor. Methods for preventing the leakage current of a pull-up PMOS transistor have been studied. However, these conventional methods need additional pads or transistors connected in complicated ways. Moreover, some of the conventional methods increase I/O pad loading and pull-up gate loading, which may decrease I/O interface speed.
The reliability of a gate oxide is decreased since an excessively high electronic field is formed at the gate oxide. While a dual-oxide process can address the reliability problem, a transistor having a thick gate oxide may decrease I/O interface speed. To provide gate-oxide reliability in a pull-up transistor without decreasing the I/O interface speed, gate tracking has been introduced. To avoid reliability problems related with a pull-down transistor and a receiver, a method of connecting in series additional N-type metal-oxide semiconductor (NMOS) transistors whose gates are connected to a power supply is usually used. However, it becomes difficult to limit the swing level of a receiving signal in the additional NMOS transistors in a low power supply voltage environment or a low-voltage operating environment.
Hot-carrier injection occurs when there is a large voltage difference between a drain and a source. A stacked NMOS transistor and a blocking transistor, each of which is connected in series with a pull-down transistor, prevent hot-carrier injection to the pull-down transistor. However, these transistors may undergo hot-carrier injection when a receiving mode is converted into a transmission mode. Accordingly, to reduce an excessively high voltage or a high potential charge accumulated at an I/O pad in the receiving mode, a hot-carrier protection circuit is required.
To address the above-described concerns that may occur in a mixed interface system and to support a low operating voltage, new mixed-voltage interfacing is needed.